Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis

This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

[1]  Claude Thibeault,et al.  Multi-abstraction level signature generation and comparison based on radiation single event upset , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[2]  R. Velazco,et al.  Single-event-upset-like fault injection: a comprehensive framework , 2005, IEEE Transactions on Nuclear Science.

[3]  Mengu Cho,et al.  Evaluation of SRAM based FPGA performance by simulating SEU through fault injection , 2013, 2013 6th International Conference on Recent Advances in Space Technologies (RAST).

[4]  Alan D. George,et al.  Acceleration of FPGA Fault Injection Through Multi-Bit Testing , 2010, ERSA.

[5]  Andrea Domenici,et al.  Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs , 2013, ACM Great Lakes Symposium on VLSI.

[6]  Andrea Domenici,et al.  SEU-X: A SEu un-excitability prover for SRAM-FPGAs , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

[7]  Massimo Violante,et al.  Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs , 2007, 12th IEEE European Test Symposium (ETS'07).

[8]  Luigi Carro,et al.  On the optimal design of triple modular redundancy logic for SRAM-based FPGAs , 2005, Design, Automation and Test in Europe.

[9]  Yvon Savaria,et al.  On Extra Delays Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiation , 2014, IEEE Transactions on Nuclear Science.

[10]  Paolo Prinetto,et al.  A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[11]  Wai Chong Chia,et al.  An automated approach for locating multiple faulty LUTs in an FPGA , 2008, Microelectron. Reliab..

[12]  J.N. Tombs,et al.  FT-UNSHADES-uP: A platform for the analysis and optimal hardening of embedded systems in radiation environments , 2008, 2008 IEEE International Symposium on Industrial Electronics.

[13]  Y. Savaria,et al.  On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations , 2012, IEEE Transactions on Nuclear Science.

[14]  Raoul Velazco,et al.  A new fault injection approach to study the impact of bitflips in the configuration of SRAM-based FPGAs , 2011, Int. Arab J. Inf. Technol..

[15]  G. Sorrenti,et al.  Using FLIPPER to Predict Proton Irradiation Results for VIRTEX 2 Devices: A Case Study , 2009, IEEE Transactions on Nuclear Science.