Contributions to the evaluation of ensembles of combinational logic gates

This work presents an effective way for evaluating and validating ensembles of combinational CMOS gates and logic cell libraries. The major contributions include an innovative design methodology for such a kind of test vehicle, as well as a simple and flexible multi-operating mode circuit architecture. The resulting circuit is quite useful for cell library verification at different levels: in the EDA environment and on silicon prototyping. The proposed methodology can be applied for analysis taking into account the logic gate functionality, timing performance, power consumption and circuit operating impact of nanometer aging effects. Simulation results demonstrate the circuit operation, features and facilities described herein.