Accelerating Simulation with FPGAs
暂无分享,去创建一个
Joel Emer | Michael Adler | Michael Pellauer | Angshuman Parashar | A. Parashar | J. Emer | Michael Pellauer | Michael Adler
[1] Arvind,et al. A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs , 2008, FPGA '08.
[2] M.M. Denneau. The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.
[3] Dam Sunwoo,et al. The FAST methodology for high-speed SoC/computer simulation , 2007, ICCAD 2007.
[4] Dam Sunwoo,et al. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators , 2007, MICRO.
[5] Arvind,et al. A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs , 2009, TRETS.
[6] David I. August,et al. Exploiting parallelism and structure to accelerate the simulation of chip multi-processors , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..
[7] Arvind,et al. Bounded Dataflow Networks and Latency-Insensitive circuits , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.
[8] Babak Falsafi,et al. A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs , 2008, FPGA '08.
[9] Christoforos E. Kozyrakis,et al. RAMP: Research Accelerator for Multiple Processors , 2007, IEEE Micro.
[10] Arvind,et al. Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs , 2008, ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software.
[11] Ian Page. Constructing hardware-software systems from a single description , 1996, J. VLSI Signal Process..
[12] David A. Patterson,et al. RAMP gold: An FPGA-based architecture simulator for multiprocessors , 2010, Design Automation Conference.