Test Resource Partitioning for System-on-a-Chip

Preface. Part I: Introduction. 1. Test Resource Partitioning. Part II: TRP for Test Hardware Optimization. 2. Test Access Mechanism Optimization. 3. Improved Test Bus Partitioning. 4. Test Wrapper and Tam Co-Optimization. Part III: TRP for Testing Time Minimization. 5. Test Scheduling. 6. Precedence, Preemption, and Power Constraints. Part IV: TRP for Test Data Volume Reduction. 7. Test Data Compression Using Golomb Codes. 8. Frequency-Directed Run-Length (FDR) Codes. 9. TRP for Low-Power Scan Testing. 10. Conclusion. References. Index.