Evaluation of 15 kV SiC N-IGBT and P-IGBT for complementary inverter topology with zero dv/dt stress on gate drivers

The complementary inverter topology with N-channel and P-channel switching devices is a known method of eliminating dv/dt stress on the gate drivers. In the Silicon (Si) based applications, this advantage did not gain wide attention due to inherent inefficiency of the P-type devices, and the matured technology to handle the dv/dt stress levels produced by these devices with highest blocking voltage rating of 6.5 kV. On the other hand, the ultrahigh voltage (> 12 kV) SiC devices generate high dv/dt due to their high speed switching. This requires meticulous design of the gate drivers for reliable operation of high power converters. As an easy alternative, the option of using a complementary inverter has been explored in this paper. Both N-channel and P-channel IGBTs with blocking capability of 15 kV have been investigated for the complementary structure. The N-IGBT is found to be more efficient than the P-IGBT, based on the experimental switching characterization results at 6 kV and 5 A. The results of the 3 kV half-bridge complementary inverter prototype are also presented. The option of trade-off of P-IGBT field-stop buffer layer parameters (thickness, doping concentration and lifetime) for better switching characteristics can provide the use of complementary topologies a promising alternative for high power conversion.