Characteristics of ESD protection devices operated under elevated temperatures

In this paper, characteristics of electrostatic discharge (ESD) protection devices operating under various ambient temperatures are investigated. The devices considered are diodes and silicon controlled rectifiers (SCRs) including Lateral SCR (LSCR) and P-Substrate Triggered SCR (PSTSCR) fabricated in a 0.35 um BCD (Bipolar-CMOS-DMOS) technology. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) tester and the Signatone S1060 heating module, and the TLP I-V characteristics are analyzed in details.

[1]  Hyun-Young Kim,et al.  The design of SCR-based dual direction ESD protection circuit with low trigger voltage , 2014, 2014 International SoC Design Conference (ISOCC).

[2]  Manoj Sachdev,et al.  ESD Protection Device and Circuit Design for Advanced CMOS Technologies , 2008 .

[3]  Yil Suk Yang,et al.  Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures , 2010 .

[4]  M. Bafleur,et al.  High-temperature operation MOS-IGBT power clamp for improved ESD protection in smart power SOI technology , 2011, EOS/ESD Symposium Proceedings.

[5]  Juin J. Liou,et al.  ESD Design and Analysis Handbook , 2003 .

[6]  G. Meneghesso,et al.  Development of a new high holding voltage SCR-based ESD protection structure , 2008, 2008 IEEE International Reliability Physics Symposium.

[7]  Juin J. Liou,et al.  No-Snapback Silicon-Controlled Rectifier for Electrostatic Discharge Protection of High-Voltage ICs , 2015, IEEE Electron Device Letters.

[8]  Sheng-Lyang Jang,et al.  Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits , 2000 .

[9]  S. Sze.  Semiconductor Devices: Physics and Technology , 1985 .

[10]  Javier A. Salcedo,et al.  Design of a low leakage ESD clamp for high voltage supply in 65nm CMOS technology , 2014, 2014 IEEE International Reliability Physics Symposium.

[11]  Ming-Dou Ker,et al.  Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process , 2003 .

[12]  Yan Han,et al.  A novel SCR for ESD protection in ICs , 2007, 2007 7th International Conference on ASIC.

[13]  Ming-Hsiang Song,et al.  Bias Temperature Stress (BTS) induced ESD device's leakage issue and Its preventing solutions in smart power technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[14]  Sheng-Lyang Jang,et al.  Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection circuits , 2001 .

[15]  Juin J. Liou,et al.  Silicon-Controlled Rectifier for Electrostatic Discharge Protection Solutions With Minimal Snapback and Reduced Overshoot Voltage , 2015, IEEE Electron Device Letters.

[16]  Chung-Yu Wu,et al.  Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI , 1996 .

[17]  Juin J. Liou,et al.  Characteristics of ESD protection devices operated under elevated temperatures , 2016 .

[18]  Jeff Watson,et al.  High-Temperature Electronics Pose Design and Reliability Challenges , 2012 .

[19]  Yong-Seo Koo,et al.  Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures , 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.

[20]  Manoj Sachdev,et al.  Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment , 2005, Sixth international symposium on quality electronic design (isqed'05).

[21]  Ming-Dou Ker,et al.  Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger , 2000 .