Design-hierarchy aware mixed-size placement for routability optimization

Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.

[1]  Jarrod A. Roy,et al.  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Jin Hu,et al.  Completing high-quality global routes , 2010, ISPD '10.

[3]  Volker Heun,et al.  Theoretical and Practical Improvements on the RMQ-Problem, with Applications to LCA and LCE , 2006, CPM.

[4]  Andrew B. Kahng,et al.  A semi-persistent clustering technique for VLSI circuit placement , 2005, ISPD '05.

[5]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Martin D. F. Wong,et al.  Design hierarchy-guided multilevel circuit partitioning , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Chris C. N. Chu,et al.  Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design , 2005, ISPD '05.

[8]  Chris C. N. Chu,et al.  Handling complexities in modern large-scale mixed-size placement , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[9]  Joseph R. Shinnerl,et al.  mPL6: enhanced multilevel mixed-size placement , 2006, ISPD '06.

[10]  Yao-Wen Chang,et al.  Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[11]  Jarrod A. Roy,et al.  Min-cut floorplacement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Andrew B. Kahng,et al.  Implementation and extensibility of an analytic placer , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Patrick Groeneveld,et al.  Probabilistic congestion prediction , 2004, ISPD '04.

[14]  Jarrod A. Roy,et al.  High-Performance Routing at the Nanometer Scale , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Yao-Wen Chang,et al.  Metal-Density-Driven Placement for CMP Variation and Routability , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.