A Low-Voltage 42.4G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer

Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing singleended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit writebus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth. key words: frame-bu er, embedded-DRAM, 3D, high bandwidth

[1]  Masaki Tsukude,et al.  High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's , 1997 .

[2]  T. Furuyama,et al.  A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM , 1995 .

[3]  T. Furuyama,et al.  A 1.6 GB/s data-transfer-rate 8 Mb embedded DRAM , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[4]  Narita,et al.  An Access-sequence Control Scheme To Enhance Random Access Performance Of Embedded DRAMs , 1997 .

[5]  Makoto Taniguchi,et al.  Large Scale Embedded DRAM Technology(Special Issue on Multimedia, Network, and DRAM LSIs) , 1998 .

[6]  Y. Nakagome,et al.  A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[7]  Hiroyuki Kawai,et al.  A 10 Mb frame buffer memory with Z-compare and A-blend units , 1995, IEEE J. Solid State Circuits.

[8]  P. DeMone,et al.  A 33 GB/s 13.4 Mb integrated graphics accelerator and frame buffer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).