Voltage domain correction technique for timing skew errors in time interleaved ADCs

A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction voltage at the input sampling network in a TI-ADC. The effectiveness of the technique is demonstrated by using behavioral models of a 14-bit 500MS/s 2 channel TI-pipelined-ADC.