Column selection circuit capable of minimising load of data input/output line and semiconductor memory device having the same and semiconductor layout method thereof

PURPOSE: A column select circuit is provided to be capable of minimizing loading of a data input/output line. CONSTITUTION: A column select circuit comprises the first, second and third select parts(122,123,126). The first select parts(122) connect 32 bit line pairs of a bank(RB1) to the first data line parts(FDL) in response to bank select signals(PCBSEL1) indicating that the bank(RB1) is selected. The second select parts(124) connect ones corresponding to a column select signal(CSLi) among the first data line pairs(FDL), which are transferred from the first select parts(122), to the second data line pair(SDL) in response to the column select signal indicating addresses of bit lines in a bank(RB1). The third select part(126) connects the second data line pair(SDL) selected by the second select parts(124) to a data input/output line pair(IO,/IO) in response to a bank select signal(PCBSEL1).