Fine-grain reconfigurable logic cells based on double-gate CNTFETs

This paper presents 2-inputs cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [1] described a dynamic logic cell generating only 14 functions instead of 16 normally performed by the multiplexer-based logic part of a CLB (Configurable Logic Block) of an FPGA for 2-inputs. In this work, a reconfigurable 2-input dynamic logic cell designed using DG-CNTFET devices is able to achieve the whole set of 16 functions exploiting a specific correlation between input and configuration signals to offer full functionality over previous version. We also built a reconfigurable 2-input static logic cell which performs 16 functions. Both cells demonstrate a significant reduction in circuit complexity with respect to conventional CMOS-based reconfigurable cells for equivalent functionality. Compared with a 2-LUT, the dynamic cell improve the time delay by a factor of 2X to the detriment of 2X increase in power consumption, while the static logic cell shows an improvement of 2X in term of power consumption and time delay.

[1]  Ian O'Connor,et al.  Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs , 2008, VLSI-SoC.

[2]  C. Tretz,et al.  Novel high-density low-power high-performance double-gate logic techniques , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[3]  Giovanni De Micheli,et al.  Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[5]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[6]  Jie Liu,et al.  Selective growth of well-aligned semiconducting single-walled carbon nanotubes. , 2009, Nano letters.

[7]  Sinan Kaptanoglu,et al.  Improving FPGA Performance and Area Using an Adaptive Logic Module , 2004, FPL.

[8]  J. Colinge Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[9]  Kaushik Roy,et al.  Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET , 2005, Sixth international symposium on quality electronic design (isqed'05).

[10]  Paul Beckett A fine-grained reconfigurable logic array based on double gate transistors , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[11]  Fabien Clermidy,et al.  Reducing transistor count in clocked standard cells with ambipolar double-gate FETs , 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

[12]  Frédéric Gaffiot,et al.  CNTFET Modeling and Reconfigurable Logic-Circuit Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  I. Hassoune,et al.  Double-gate MOSFET based reconfigurable cells , 2007 .

[14]  M. Lundstrom,et al.  Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays , 2004, cond-mat/0406494.

[15]  P. Avouris,et al.  Novel carbon nanotube FET design with tunable polarity , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[16]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[17]  Kaushik Roy,et al.  Double-gate SOI devices for low-power and high-performance applications , 2005, ICCAD.

[18]  I. O'Connor,et al.  On the performance of double-gate MOSFET circuit applications , 2007, 2007 IEEE Northeast Workshop on Circuits and Systems.

[19]  T. Dao Advanced double-gate fully-depleted silicon-on-insulator (DG-FDSOI) device and device impact on circuit design & power management , 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

[20]  Jerry G. Fossum,et al.  Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current , 1999 .