Study on line edge roughness for electron beam acceleration voltages from 50to5kV

Electrical characteristics of devices depend on the line edge roughness (LER). LER contributes to the off-state leakage budget and short-channel effect. Therefore, it has to be controlled during the lithography step since it strongly impacts the final component’s roughness. This work aims at the characterization of LER dependence on the beam acceleration voltage. Usually publications consider many lithography parameters that can influence LER. Different resists were exposed to beam acceleration voltage from 5to50kV. Thus, only two parameters that influence LER varied during experiments for a given resist: the exposure dose (i.e., shot noise) and the spot size. Then, simulations were carried out with those parameter variations. The impact of other LER contributors was considered as constant. Comparison between model and experimental results allows one to link resist sensitivity, exposure time, and LER.

[1]  C.H. Diaz,et al.  An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.

[2]  M. Ercken,et al.  Determining the impact of statistical fluctuations on resist line edge roughness , 2005 .

[3]  Remco Jager,et al.  Optimum dose for shot noise limited CD uniformity in electron-beam lithography , 2004 .

[4]  Yongdae Kim,et al.  EUV mask inspection tool using high NA DUV inspection tool , 2008, SPIE Advanced Lithography.

[5]  Ralph R. Dammel,et al.  Possible Origins and Some Methods to Minimize LER , 2005 .

[6]  Henry I. Smith A statistical analysis of ultraviolet, x-ray, and charged-particle lithographies , 1986 .

[7]  Kim Y. Lee,et al.  Multiple electron-beam lithography , 2001 .

[8]  Theodore H. Fedynyshyn,et al.  Contributions of resist polymers to innate material roughness , 2008 .

[9]  C. Hohle,et al.  High throughput maskless lithography: low voltage versus high voltage , 2008, SPIE Advanced Lithography.

[10]  S. W. H. K. Steenbrink,et al.  Mapper: High troughput maskless lithography , 2008 .

[11]  P. Kruit,et al.  Local critical dimension variation from shot-noise related line edge roughness , 2005 .

[12]  P. Fisher,et al.  Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices? , 2004, IEEE Transactions on Semiconductor Manufacturing.

[13]  P. A. Orphanos,et al.  Roughness study of a positive tone high performance SCALPEL resist , 2000 .