New Divider Design for Stochastic Computing

Stochastic computing (SC) is an unconventional computing paradigm which enables low power and massive parallelism in various applications. The numerical values in SC are represented as random bit-streams and interpreted as probabilities. The SC design provides the low-cost arithmetic units, while suffering from long latency and accuracy degradation. The division operation is the most challenging in SC. Chen et al. have recently developed a stochastic divider, called correlated divider (CORDIV), by exploiting the conditional probability. It has been proved that the CORDIV has a lower hardware cost than the previous designs and provides good accuracy performance. This brief presents a new stochastic divider, which includes one saturating subtractor and one JK flip flop. The subtractor is designed by taking advantage of correlation among inputs. Simulation results reveal that the proposed divider has the same accuracy performance as CORDIV. However, the new divider has competitive advantages over CORDIV. With applications to the piecewise linear function implementation, the proposed design is superior to the finite state machine (FSM)-based method in terms of accuracy and hardware cost.

[1]  John P. Hayes,et al.  Exploiting correlation in stochastic circuit design , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

[2]  Keshab K. Parhi,et al.  Computing Arithmetic Functions Using Stochastic Logic by Series Expansion , 2019, IEEE Transactions on Emerging Topics in Computing.

[3]  Naoya Onizawa,et al.  An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage–Frequency–Length Scaling , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[4]  Hsie-Chia Chang,et al.  A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Keshab K. Parhi,et al.  Successive cancellation decoding of polar codes using stochastic computing , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  Jianhao Hu,et al.  A Low Complexity Sparse Code Multiple Access Detector Based on Stochastic Computing , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  John P. Hayes,et al.  Design of Division Circuits for Stochastic Computing , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[8]  Fabrizio Lombardi,et al.  An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[9]  Olivier Sentieys,et al.  Taking advantage of correlation in stochastic computing , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[10]  John P. Hayes,et al.  Survey of Stochastic Computing , 2013, TECS.

[11]  Kia Bazargan,et al.  Computation on Stochastic Bit Streams Digital Image Processing Case Studies , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Naoya Onizawa,et al.  VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Keshab K. Parhi,et al.  Stochastic Logic Implementations of Polynomials With All Positive Coefficients by Expansion Methods , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Brian R. Gaines,et al.  Stochastic Computing Systems , 1969 .

[15]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[16]  Jianhao Hu,et al.  A Fast Converging Normalization Unit for Stochastic Computing , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Armin Alaghi,et al.  Correlation manipulating circuits for stochastic computing , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Jianhao Hu,et al.  Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Indrajit Chakrabarti,et al.  A Parallel Stochastic Number Generator With Bit Permutation Networks , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.