High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis

Image scaling is a fundamental algorithm used in a large range of digital image applications. In this paper, we propose an efficient VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved design productivity compared to the traditional RTL-based design flow. So we explored a large design space including several fine-grained and coarse-grained optimizations in the pipeline architecture design. Our architecture is verified in a working system based on Xilinx Kintex-7 FPGA. Experiments show that our design can process UHD (3840*2160) videos at 30fps with moderate resource utilization.