A pipeline memory-efficient programmable architecture for the 2D discrete wavelet transform using lifting scheme

In this paper we propose a dedicated architecture to implement a 2-D Discrete Wavelet Transform (DWT) by using the lifting scheme method. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. The proposed architecture is re-configurable for 5/3 and 9/7 filters and employs folded configuration to reduce the hardware cost and achieve higher hardware utilization. The architecture is useful for VLSI implementation and various image- video applications. The design has been modeled by VHDL language and simulated by Modelsim and it is fully synthesizable.