Application performance improvement by exploiting process variability on FPGA devices

Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure involving a wide network of customized ring oscillators to measure intra-chip and inter-chip variability in 28nm FPGAs, i.e., in eight Xilinx Zynq XC7Z020T-1CSG324 devices. Second, we develop a closed-loop framework based on dynamic reconfiguration of clock tiles, I/O data sniffing, HW/SW communication, and verification with test vectors, to dynamically increase the operating frequency in Zynq while preserving its correctness. Our results show intra-chip variability in the area of 5.2% to 7.7% and inter-chip variability up to 17%. Our framework improves the performance of example FIR designs by up to 90.3% compared to the SW tool reports and shows speed difference among devices by up to 12.4%.

[1]  Theerayod Wiangtong,et al.  International Conference on Field Programmable Technology , 2006 .

[2]  Peter Y. K. Cheung,et al.  Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[3]  Li Shang,et al.  Reliability- and process variation-aware placement for FPGAs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[4]  Steven Trimberger,et al.  Analysis of within-die process variation in 65nm FPGAs , 2011, 2011 12th International Symposium on Quality Electronic Design.

[5]  S. Minehane,et al.  Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies , 2008, IEEE Transactions on Electron Devices.

[6]  Sani R. Nassif,et al.  Design for Manufacturability and Statistical Design: A Comprehensive Approach , 2006 .

[7]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[8]  Mohammad Hosseinabady,et al.  Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling , 2016, IEEE Transactions on Computers.

[9]  Farid N. Najm,et al.  An adaptive FPGA architecture with process variation compensation and reduced leakage , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  Davide Bertozzi,et al.  Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[11]  Sani R. Nassif,et al.  Design for Manufacturability and Statistical Design - A Constructive Approach , 2007, Series on integrated circuits and systems.

[12]  Puneet Gupta,et al.  On the efficacy of NBTI mitigation techniques , 2011, 2011 Design, Automation & Test in Europe.

[13]  Francky Catthoor,et al.  Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory , 2014, IEEE Transactions on Device and Materials Reliability.

[14]  John P. Hayes,et al.  On-line sensing for healthier FPGA systems , 2010, FPGA '10.

[15]  S. Hamdioui,et al.  Why is CMOS scaling coming to an END? , 2008, 2008 3rd International Design and Test Workshop.

[16]  George A. Constantinides,et al.  Accuracy-Performance Tradeoffs on an FPGA through Overclocking , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[17]  Sani R. Nassif,et al.  Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues , 2012, 17th Asia and South Pacific Design Automation Conference.