Buried power rail integration for CMOS scaling beyond the 3 nm node

As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.