Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips
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A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
[1] P. Thieberger,et al. Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM , 1985, IEEE Transactions on Nuclear Science.
[2] A.M. Mohsen,et al. Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-well protection barrier on VLSI memories , 1985, IEEE Transactions on Electron Devices.