D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems
暂无分享,去创建一个
[1] Alberto L. Sangiovanni-Vincentelli,et al. Synthesis of Multitask Implementations of Simulink Models With Minimum Delays , 2010, IEEE Transactions on Industrial Informatics.
[2] Marco D. Santambrogio,et al. Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] María José Moure,et al. Features, Design Tools, and Application Domains of FPGAs , 2007, IEEE Transactions on Industrial Electronics.
[4] Marco D. Santambrogio,et al. Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse , 2009, GLSVLSI '09.
[5] Jürgen Becker,et al. Operating System for Runtime Reconfigurable Multiprocessor Systems , 2011, Int. J. Reconfigurable Comput..
[6] François Duhem,et al. FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA , 2011, ARC.
[7] Seda Ogrenci Memik,et al. Placement and Floorplanning in Dynamically Reconfigurable FPGAs , 2010, TRETS.
[8] Marco D. Santambrogio,et al. An application-centered design flow for self reconfigurable systems implementation , 2009, 2009 Asia and South Pacific Design Automation Conference.
[9] Scott Hauck,et al. Reconfigurable computing: a survey of systems and software , 2002, CSUR.
[10] Marco D. Santambrogio,et al. Dynamic Reconfigurability in Embedded System Design , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[11] Alberto L. Sangiovanni-Vincentelli,et al. Optimal Synthesis of Communication Procedures in Real-Time Synchronous Reactive Models , 2010, IEEE Transactions on Industrial Informatics.