Asynchronous sense differential logic

Charge-recycling differential logic (CRDL) implements energy-efficient operation by recycling already used charge. This technique requires p-channel devices with higher threshold for maximum efficiency. Half-rail differential logic (HRDL) avoids the drawback at the expense of performance. These circuits are prone to pre-evaluation discharge during evaluation when not properly designed. Asynchronous sense differential logic (ASDL) improves energy efficiency with no threshold change or performance degradation.

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[3]  Kwyro Lee,et al.  Charge recycling differential logic for low-power application , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.