A 200MSPS time-interleaved 12-bit ADC system with digital calibration

This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array (FPGA). Experimental results demonstrate that the proposed calibration technique allows an SNDR improvement of 26dB for just 32 iterations of calibration.

[1]  Mikko Valkama,et al.  Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  P.J. Hurst,et al.  A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  José Silva-Martínez,et al.  A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration , 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

[4]  M El-Chammas,et al.  A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration , 2011, IEEE Journal of Solid-State Circuits.

[5]  Yue Shi,et al.  A modified particle swarm optimizer , 1998, 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360).

[6]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Lawrence T. Pileggi,et al.  A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI , 2014, IEEE Journal of Solid-State Circuits.

[8]  Behzad Razavi,et al.  Design Considerations for Interleaved ADCs , 2013, IEEE Journal of Solid-State Circuits.

[9]  Lawrence T. Pileggi,et al.  22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[10]  Jean-François Naviner,et al.  Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.