The SpecSyn Design Process and Human Interface

This report describes a presentation on the design methodology and the user's view of the SpecSyn system design framework. Given an abstract speci cation of a system, we present speci cation capture and the subsequent re nements that will result in synthesizable descriptions. The advantages of the underlying methodology compared to current approaches are highlighted.

[1]  Daniel Gajski,et al.  System clock estimation based on clock slack minimization , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[2]  Frank Vahid,et al.  Obtaining functionally equivalent simulations using VHDL and a time-shift transformation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  Daniel D. Gajski,et al.  SpecCharts : A Language for System Level Synthesis , 1991 .

[4]  Frank Vahid,et al.  Specification partitioning for system design , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[5]  Frank Vahid,et al.  A survey of behavioral-level partitioning systems , 1991 .

[6]  Daniel D. Gajski,et al.  Synthesis from VHDL , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[7]  Frank Vahid,et al.  System specification and synthesis with the SpecCharts language , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[8]  Frank Vahid,et al.  Modeling with SpecCharts , 1990 .

[9]  Daniel D. Gajski,et al.  Constant-time cost evaluation for behavioral partitioning , 1992 .

[10]  Roger Lipsett,et al.  VHDL: hardware description and design , 1989 .