Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores

Motivated by the presence of mega-cores in hierarchical systems-on-a-chip, This work describes a new framework for the design space exploration of multi-level test access mechanisms. Test resources are placed next to the mega-core wrappers, which removes the constraint that upper-level TAM width must be wider than the internal TAM width of the mega-core. The proposed solution can rapidly analyze the tradeoffs between test application time and area overhead and it facilitates test data reuse for hard mega-cores.