3D-NAND cell challenges to enable high density and high-Performance devices

3D-NAND array density has been increasing by 8-10X in the past 5 year, hitting 10Gb/mm2 [1], thanks to CMOS under the array and WLs stacking. Cell scaling in vertical direction has been a key enabler, especially for charge trap cell, due to easier process integration, but it impacts both intrinsic cell functionality and process variations, challenging NAND array reliability and performances. Maintaining or improving products specifications over technology nodes while scaling the cell requires a joined effort of process integration, design and system.