Design of low-complexity and high-speed digital Finite Impulse Response filters
暂无分享,去创建一个
Levent Aksoy | Paulo F. Flores | José C. Monteiro | Eduardo Costa | Diego Jaccottet | P. Flores | E. Costa | J. Monteiro | L. Aksoy | Diego Jaccottet
[1] Ryan Kastner,et al. Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[2] Levent Aksoy,et al. Search algorithms for the multiple constant multiplications problem: Exact and approximate , 2010, Microprocess. Microsystems.
[3] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[4] José C. Monteiro,et al. A new architecture for signed radix-2/sup m/ pure array multipliers , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[5] Markus Püschel,et al. Multiplierless multiple constant multiplication , 2007, TALG.
[6] Levent Aksoy,et al. Area optimization algorithms in high-speed digital FIR filter synthesis , 2008, SBCCI '08.
[7] Andrew G. Dempster,et al. Multiplier blocks using carry-save adders , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[8] Earl E. Swartzlander,et al. High radix booth multipliers using reduced area adder trees , 1994, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers.
[9] D. H. Jacobsohn,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[10] Hyeong-Ju Kang,et al. Digital filter synthesis based on minimal signed digit representation , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[11] Philip Heng Wai Leong,et al. Mullet - a parallel multiplier generator , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[12] H. T. Nguyen,et al. Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[13] K. Steiglitz,et al. Some complexity issues in digital signal processing , 1984 .
[14] H. Samueli,et al. Design techniques for silicon compiler implementations of high-speed FIR digital filters , 1996 .
[15] Lars Wanhammar,et al. Bit-Level Optimization of Shift-and-Add Based FIR Filters , 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.
[16] A. Dempster,et al. Use of minimum-adder multiplier blocks in FIR digital filters , 1995 .
[17] R. Hartley. Subexpression sharing in filters using canonic signed digit multipliers , 1996 .
[18] Milos D. Ercegovac,et al. Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.
[19] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[20] Levent Aksoy,et al. Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Henrik Ohlsson,et al. Minimum-adder integer multipliers using carry-save adders , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).