Fault impact and fault tolerance in multiprocessor interconnection networks

Growing complexity of parallel machines coupled with increasing chip densities escalates the need for fault tolerance and recovery in these systems. In pursuit of the goal of fault-tolerant multiprocessors, many techniques have been proposed. Since methods for designing fault-tolerant processors and memories are relatively mature, the techniques considered in this paper focus on the interconnection network (ICN) linking the processors. The impact of faults on non-fault-tolerant ICNs is contrasted with that in fault-tolerant networks. Fault tolerance in ICNs is addressed at two levels, inter-node or switch level and system level. Inter-node or switch level pertains to data and control integrity and system level deals with maintaining network connectivity and adequate performance levels in the presence of faults. Fault-tolerant schemes at the switching element level warrant some form of concurrent error detection such as the use of codes usually combined with a full handshake protocol. Space–time trade-offs involved in the use of various codes and protocols are investigated. At the system level, several augmented multi-stage switching ICNs, tree and ring networks are studied. The combined provision for fault tolerance together with improved performance in the non-fault condition is emphasized. Finally, strategies for network reconfiguration and rerouting after system failure are presented.