An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

Distributed charge injection (CI) scheme featuring distributed <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {MAX}}$ </tex-math></inline-formula>-complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {CC}}$ </tex-math></inline-formula> for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of ~11% over a guard-banded baseline.