Formal Proof for a General Architecture of Hybrid Prefix/Carry-Select Adders
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[1] Akhilesh Tyagi,et al. A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.
[2] Ralf Hinze. An Algebra of Scans , 2004, MPC.
[3] Yuke Wang,et al. The design of hybrid carry-lookahead/carry-select adders , 2002 .
[4] Israel Koren. Computer arithmetic algorithms , 1993 .
[5] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[6] Kevin J. Nowka,et al. A fast hybrid carry-lookahead/carry-select adder design , 2001, GLSVLSI '01.
[7] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[8] Vitit Kantabutra. A Recursive Carry-Lookahead/Carry-Select Hybrid Adder , 1993, IEEE Trans. Computers.
[9] Mary Sheeran. Hardware Design and Functional Programming: a Perfect Match , 2005, J. Univers. Comput. Sci..
[10] Gudula Rünger,et al. Derivation of a logarithmic time carry lookahead addition circuit , 2004, J. Funct. Program..
[11] Deepak Kapur,et al. Mechanical Verification of Adder Circuits using Rewrite Rule Laboratory , 1998, Formal Methods Syst. Des..
[12] Earl E. Swartzlander,et al. A Spanning Tree Carry Lookahead Adder , 1992, IEEE Trans. Computers.
[13] Feng Liu,et al. Proofs of Correctness and Properties of Integer Adder Circuits , 2010, IEEE Transactions on Computers.
[14] Khaled Elleithy,et al. A rule-based approach for high speed adders design verification , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.
[15] Glen Stone,et al. THE IMPLEMENTATION AND VERIFICATION OF A CONDITIONAL SUM ADDER , 1988 .
[16] R. G. Deshmukh,et al. A novel scheme for irregular parallel-prefix adders , 1997, Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century'.
[17] Xiao Yan Yu,et al. A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.