Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters

This paper presents a new capacitor array structure and its switch control method for binary weighted SAR analog- to-digital converters, which can significantly lower the energy consumed in charge redistribution steps. The proposed method is analyzed theoretically and simulations are performed to verify the theoretical analysis. Simulation results show that the proposed capacitor array structure and switching method can reduce the average energy consumed in the capacitor array by 75% and 60% compared to the conventional method and the splitting capacitor method, respectively.

[1]  B.P. Ginsburg,et al.  500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , 2007, IEEE Journal of Solid-State Circuits.

[2]  L. R. Carley,et al.  An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC , 1995 .

[3]  Brian P. Ginsburg,et al.  An energy-efficient charge recycling approach for a SAR converter with capacitive DAC , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[5]  K. Uyttenhove,et al.  A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.

[6]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[7]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  P. Gray,et al.  All-MOS charge redistribution analog-to-digital conversion techniques. I , 1975, IEEE Journal of Solid-State Circuits.