IRT: A modeling system for single event upset analysis that captures charge sharing effects
暂无分享,去创建一个
William G. Bennett | Shashank Gupta | Norbert Seifert | Kerryann Foley | Jyothi B. Velamala | N. Seifert | J. Velamala | Shashank Gupta | K. Foley | W. G. Bennett
[1] Norbert Seifert,et al. Radiation-induced Soft Errors: A Chip-level Modeling Perspective , 2010, Found. Trends Electron. Des. Autom..
[2] Changhong Dai,et al. Circuit-level modeling of soft errors in integrated circuits , 2005, IEEE Transactions on Device and Materials Reliability.
[3] S. Incerti,et al. Geant4 developments and applications , 2006, IEEE Transactions on Nuclear Science.
[4] Y. Tosaka,et al. Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems , 1999 .
[5] R. Allmon,et al. On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies , 2010, 2010 IEEE International Reliability Physics Symposium.
[6] G. R. Srinivasan,et al. Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..
[7] Henry H. K. Tang,et al. SEMM-2: A new generation of single-event-effect modeling tools , 2008, IBM J. Res. Dev..
[8] Ivan R. Linscott,et al. LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.
[9] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[10] Shusuke Yoshimoto,et al. Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure , 2011, 2011 IEEE 17th International On-Line Testing Symposium.
[11] A. Eremenko,et al. MDS — A New, Highly Extensible Device Simulator , 2007 .
[12] Guillaume Hubert,et al. Detailed analysis of secondary ions' effect for the calculation of neutron-induced SER in SRAMs , 2001 .
[13] Philippe Roche,et al. Soft-Error Rate of Advanced SRAM Memories: Modeling and Monte Carlo Simulation , 2012 .
[14] K. Soumyanath,et al. Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[15] J. Holmes,et al. A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit , 2009, IEEE Transactions on Nuclear Science.
[16] N. Seifert,et al. Robust system design with built-in soft-error resilience , 2005, Computer.
[17] S. Cea,et al. Challenges in 3D Process Simulation for Advanced Technology Understanding , 2007 .
[18] R.A. Reed,et al. Heavy Ion Testing and Single Event Upset Rate Prediction Considerations for a DICE Flip-Flop , 2009, IEEE Transactions on Nuclear Science.
[19] R.A. Reed,et al. Integrating Circuit Level Simulation and Monte-Carlo Radiation Transport Code for Single Event Upset Analysis in SEU Hardened Circuitry , 2008, IEEE Transactions on Nuclear Science.
[20] Leo B. Freeman. Critical charge calculations for a bipolar SRAM array , 1996, IBM J. Res. Dev..
[21] F. Wrobel,et al. Anthology of the Development of Radiation Transport Tools as Applied to Single Event Effects , 2013, IEEE Transactions on Nuclear Science.
[22] R. Allmon,et al. Soft Error Susceptibilities of 22 nm Tri-Gate Devices , 2012, IEEE Transactions on Nuclear Science.
[23] P.E. Dodd,et al. Physics-based simulation of single-event effects , 2005, IEEE Transactions on Device and Materials Reliability.
[24] G. Gasiot,et al. Combining GEANT4 and TIARA for Neutron Soft Error-Rate Prediction of 65 nm Flip-Flops , 2011, IEEE Transactions on Nuclear Science.