High-density multilayer connection technology for MEMS and CMOS applications

A multi-layer technology for electrical high-density connections between the two opposing sides of a wafer has been developed. Openings in a double-side polished wafer were created by applying a deep reactive ion etching technique. Hole structures with a diameter of 20 μm were formed through a 350-μm thick wafer. A multi-layer system of up to eight layers consisting of alternating conducting layers (N-type doped poly-silicon) and isolating layers (silicon-oxide) were grown until the vias were filled. Subsequently, all layers on the wafer surface were then removed in a CMP process. In this way, a multi-connection structure embedded in the silicon wafer can be fabricated. The applied low-pressure chemical vapor deposition techniques guarantee a sufficient homogenous coating outside and inside of the entire structure to a minimum layer thickness of one µm. The connection quality has been examined combining impedance spectroscopy and Focused Ion Beam technology. Depending on the geometry and the doping profile of the poly-silicon layers, a connection resistance of less than 80 Ohms can be achieved with sufficient DC isolation. In this way, a multi-connection of up to four isolated signal lines per opening was manufactured. This corresponds to a local connection density higher than 30.000/cm2. The achievable connection density and the full CMOS compatibility of the applied processes make this multi-layer connection technology particularly well suited for combined MEMS and CMOS applications