Apparatus and method for DLL-based frequency multiplier
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The present invention relates to a frequency multiplication device and method of the delay lock loop based. Wherein the frequency multiplier unit comprises a voltage-controlled delay line and the buffer stage having an N number of delay stages, lock the last the last clock signal of the buffer stage to the reference clock signal passing through the buffer stage passing through the voltage controlled delay line, wherein in the locked state, the delay-locked loop for generating said reference clock signal N + 1 of the differential clock signal is spread evenly by the number N of the delay stages from and, passing through the buffer stage of the differential clock signal; An AND circuit for generating an output pulse from the differential clock signal passing through the output signal of the delay lock loop, said buffer stage; And Edgecomb included by thee for generating a frequency multiplier output clock by combining the output pulse. A delay locked loop, frequency multiplier, a voltage controlled delay line, the lock control, a phase detector