A new power factor correction (PFC) control method suitable for low cost DSP

One main barrier to implement digital control for power factor correction (PFC) is the limited switching frequency due to the limited processor speed. A new digital PFC control method is proposed to solve this problem. For convention digital methods, the duty cycle is calculated every switching period. The new digital PFC control method uses an optimization algorithm to generate all of the required duty cycles for one half line period at one time in advance, which is based on the input current and duty cycles in the previous half tine periods. Total Harmonic Distortion (THD), which is directly related to the power factor, is determined as the objective function. Gradient descent is used as the optimization algorithm to minimize the THD and improve the power factor. The proposed new digital PFC control strategy overcomes the problem of limited switching frequency due to limited DSP speed. Simulation results show that unity power factor is achieved using the proposed method.

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