Research on the Low Power Dissipation of Pipeline ADC

A design of 50 MHz, 10 bits, 5 V pipeline ADC is introduced in this thesis. The comparator and OTA are the main improvements aiming at realizing low power dissipation. The dynamic comparator and telescopic OTA are adopted to achieve the specification. The design is implemented under 0.5 mum CMOS technology which achieves a power dissipation of 190 mW at 50 MHz sampling rate.

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