Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance

An approach to the design of reconfigurable tree architectures is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single-chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is O(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.

[1]  Vinod K. Agarwal,et al.  A Fault-Tolerant Modular Architecture for Binary Trees , 1986, IEEE Transactions on Computers.

[2]  Robert S. Swarz,et al.  The theory and practice of reliable system design , 1982 .

[3]  Ellis Horowitz,et al.  The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI , 1981, IEEE Transactions on Computers.

[4]  Arnold L. Rosenberg,et al.  The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors , 1983, IEEE Transactions on Computers.

[5]  横矢 直和,et al.  Quadtrees and Pyramids for Pattern Recognition and Image Processing , 1981 .

[6]  David A. Patterson,et al.  X-Tree: A tree structured multi-processor computer architecture , 1978, ISCA '78.

[7]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[8]  Carlo H. Séquin,et al.  Hypertree: A Multiprocessor Interconnection Topology , 1981, IEEE Transactions on Computers.

[9]  Mikhail J. Atallah,et al.  A Generalized Dictionary Machine for VLSI , 1985, IEEE Transactions on Computers.

[10]  S. Toida,et al.  An optimal 2-FT realization of binary symmetric hierarchical tree systems , 1982, Networks.

[11]  Charles E. Leiserson,et al.  Area-Efficient VLSI Computation , 1983 .

[12]  Azriel Rosenfeld,et al.  Pattern Recognition and Image Processing , 1976, IEEE Transactions on Computers.

[13]  Jeffrey D Ullma Computational Aspects of VLSI , 1984 .

[14]  John P. Hayes,et al.  A Graph Model for Fault-Tolerant Computing Systems , 1976, IEEE Transactions on Computers.

[15]  Sally A. Browning Computations on a Tree of Processors , 1979 .

[16]  Milos D. Ercegovac,et al.  Fault Tolerance in Binary Tree Architectures , 1984, IEEE Transactions on Computers.