FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications
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Thomas Skotnicki | Rachid Bouchakour | Pascal Masson | Pascale Mazoyer | Jean-Michel Portal | Sophie Puget | Germain Bossu | Pierre Perreau | Philippe Lorenzini | Claire Fenouiller-Beranger
[1] R. Ranica,et al. An 8 Mbit DRAM design using a 1 Tbulk cell , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..