An integrated framework for high-level synthesis of self-timed circuits

Asynchronous/self-timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. They are characterized by absence of global clocking and concurrency limited only by the data and control dependencies. They offer the advantages of simpler timing, the absence of clock distribution related problems, composability, opportunities for incremental improvement, and robustness. This dissertation addresses the issues underlying automating specification-driven design of self-timed circuits. An integrated collection of tools called the hopCP Design Environment is developed that facilitates the specification, simulation, analysis, and performance-directed synthesis of self-timed circuits. hopCP is a process-oriented concurrent HDL for the specification of asynchronous systems. It is equipped with constructs for specifying communication, synchronization and concurrency explicitly. It supports multicast communication, a restricted form of distributed shared variables, and a functional sublanguage to specify computation. SHILPA is a high-level system for the automated synthesis of efficient self-timed circuits from hopCP. hopCP descriptions are translated into a graph-based intermediate form called HFG and hierarchically refined into a netlist of self-timed macromodules for an Actel FPGA realization. A flow analysis scheme is described for global optimizations such as efficient guard evaluation and resource sharing. An efficient compiled-code functional simulator for hopCP specifications, based on translating HFGs into Concurrent ML, is also developed.