On the optimal design of triple modular redundancy logic for SRAM-based FPGAs

Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.

[1]  Luigi Carro,et al.  Designing and testing fault-tolerant techniques for SRAM-based FPGAs , 2004, CF '04.

[2]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Paolo Bernardi,et al.  On the evaluation of SEU sensitiveness in SRAM-based FPGAs , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[4]  Massimo Violante,et al.  Simulation-based analysis of SEU effects in SRAM-based FPGAs , 2004, IEEE Transactions on Nuclear Science.

[5]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[6]  Anthony Salazar,et al.  Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing , 1999 .