Efficient implementations of self-checking multiply and divide arrays
暂无分享,去创建一个
[1] James E. Smith,et al. Strongly Fault Secure Logic Networks , 1978, IEEE Transactions on Computers.
[2] Niraj K. Jha. Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[3] W. W. Peterson. On Checking an Adder , 1958, IBM J. Res. Dev..
[4] Suchai Thanawastien,et al. An SFS Berger check prediction ALU and its application to self-checking processor designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Niraj K. Jha. Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] N. Kanopoulos,et al. Testing of differential cascade voltage switch (DCVS) circuits , 1990 .
[7] Michael Nicolaidis,et al. Efficient implementations of self-checking adders and ALUs , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[8] Barry K. Rosen,et al. Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits , 1985, ITC.
[9] Uwe Sparmann,et al. On the check base selection problem for fast adders , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.