Syndrome-based functional delay fault location in linear digital data-flow graphs

A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components.<<ETX>>

[1]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[2]  Kurt Keutzer,et al.  Validatable nonrobust delay-fault testable circuits via logic synthesis , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[4]  Richard Bauckham.  Text-Books , 1904 .

[5]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[6]  William C. Y. Lee,et al.  Mobile Communications Engineering , 1982 .

[7]  Richard I. Hartley,et al.  Behavioral to structural translation in a bit-serial silicon compiler , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  S. Reddy,et al.  Synthesis of combinational logic circuits for path delay fault testability , 1990, IEEE International Symposium on Circuits and Systems.

[9]  Charles R. Kime,et al.  An Abstract Model for Digital System Fault Diagnosis , 1979, IEEE Transactions on Computers.

[10]  C. V. Negoiţă,et al.  Expert systems and fuzzy systems , 1985 .

[11]  H. Morowitz.  Reference books. , 1984, Hospital practice.

[12]  Dan W. Patterson,et al.  Introduction to artificial intelligence and expert systems , 1990 .

[13]  J. Lindy.  Books , 1985, The Lancet.

[14]  Sudhakar M. Reddy,et al.  On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[15]  M.G. Bellanger,et al.  Digital processing of speech signals , 1980, Proceedings of the IEEE.

[16]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[17]  S. Koul,et al.  Stripline-Like Transmission Lines for Microwave Integrated Circuits , 1989 .

[18]  Ben Zeines.  Electronic Communications Systems , 1971 .

[19]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  R. Crutchfield,et al.  Digital satellite communications , 1979, Proceedings of the IEEE.

[21]  Jacob Savir,et al.  Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.

[22]  Abhijit Chatterjee,et al.  Rapid prototyping using high density interconnects , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[23]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[24]  Yashwant K. Malaiya,et al.  Testing for Timing Faults in Synchronous Sequential Integrated Circuits , 1983, International Test Conference.