LDPC Code for Reduced Routing Decoder
暂无分享,去创建一个
[1] A. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[2] D.J.C. MacKay,et al. Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.
[3] Tong Zhang,et al. Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).
[4] Suresh Sivakumar. VLSI implementation of encoder and decoder for low-density parity-check codes , 2001 .
[5] Rüdiger L. Urbanke,et al. Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.
[6] Naresh R. Shanbhag,et al. A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes , 2005, J. VLSI Signal Process..
[7] X. Jin. Factor graphs and the Sum-Product Algorithm , 2002 .
[8] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[9] A. Glavieux,et al. Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.
[10] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.