Optimization of Cost Function with Cell Library Placement of VLSI Circuits Using Simulated Annealing

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive solution of the cell placement technique, with emphasis on standard cell and macro cell placement using simulated annealing. The metropolis algorithm is applied to generate generations by decreasing the temperature (cooling coefficient). The state will be accepted or rejected based on energy level (cost) and finally optimum solution will be selected.

[1]  Carl Sechen.  AVERAGE INTERCONNECTION LENGTH ESTIMATION FOR RANDOM AND OPTIMIZED PLACEMENTS. , 1987 .

[2]  Michael S. Hsiao.  Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits , 2002, VLSI Design.

[3]  A. Richard Newton,et al.  Learning as applied to stochastic optimization for standard-cellplacement , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[5]  Rob A. Rutenbar,et al.  Simulated annealing algorithms: an overview , 1989, IEEE Circuits and Devices Magazine.

[6]  Carl Sechen,et al.  IMPROVED SIMULATED ANNEALING ALGORIHM FOR ROW-BASED PLACEMENT. , 1987 .

[7]  Carl Sechen,et al.  VLSI Placement and Global Routing Using Simulated Annealing , 1988 .

[8]  John A. Chandy,et al.  Parallel simulated annealing strategies for VLSI cell placement , 1996, Proceedings of 9th International Conference on VLSI Design.

[9]  Giorgio Vassallo,et al.  Monreale: a new genetic algorithm for the solution of the channel routing problem , 1991, [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications.

[10]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.

[11]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[12]  I. Mahmoud,et al.  Experimental Appraisal of Linear and Quadratic Objective Functions Effect on Force Directed Method for Analog Placement , 1994 .

[13]  Tughrul Arslan,et al.  Generating test patterns for VLSI circuits using a genetic algorithm , 1994 .

[14]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[16]  Sungho Kim,et al.  An evaluation of parallel simulated annealing strategies with application to standard cell placement , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..