Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs

The size of a diagnostic test set is significantly larger than the size of a fault detection test set. As a result, fault detection test sets may be used for initial defect diagnosis, and diagnostic tests may be added as needed to narrow down a set of candidate defect sites. Between a fault detection test set and a full diagnostic test set there is a large range of test sets that can be used for improved (initial) diagnosis. This paper describes a diagnostic test generation process that produces such a range of test sets. The process is based on a ranking of the indistinguished fault pairs according to the importance of distinguishing them. The ranking is based on the structural distance between faults. This allows failure analysis to explore fewer and more localized areas of the circuit as the size of the diagnostic test set is increased. This paper also discusses the insertion of observation points to distinguish fault pairs that remain indistinguished by a diagnostic test set. Observation point insertion uses the ranked list of indistinguished fault pairs to ensure that a limited number of observation points will address the fault pairs that are the most important to distinguish.

[1]  Irith Pomeranz,et al.  Output-Dependent Diagnostic Test Generation , 2010, 2010 23rd International Conference on VLSI Design.

[2]  Malgorzata Marek-Sadowska,et al.  Multiple fault diagnosis using n-detection tests , 2003, Proceedings 21st International Conference on Computer Design.

[3]  Thomas Bartenstein.  Panel 9 - diagnostics vs failure analysis , 2004, 2004 International Conferce on Test.

[4]  Derek Feltham,et al.  Pentium(R) Pro processor design for test and debug , 1997, Proceedings International Test Conference 1997.

[5]  Irith Pomeranz,et al.  Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Yukio Okuda.  Panel synopsis - diagnosis meets physical failure analysis: how long can we succeed? , 2004, 2004 International Conferce on Test.

[7]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[8]  Irith Pomeranz,et al.  A diagnostic test generation procedure for synchronous sequential circuits based on test elimination , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Hans-Joachim Wunderlich,et al.  Adaptive Debug and Diagnosis Without Fault Dictionaries , 2009, J. Electron. Test..

[10]  Srikanth Venkataraman,et al.  POIROT: a logic fault diagnosis tool and its applications , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[12]  Wayne M. Needham,et al.  DFT strategy for Intel microprocessors , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[13]  Ruifeng Guo,et al.  Enhancing Transition Fault Model for Delay Defect Diagnosis , 2008, 2008 17th Asian Test Symposium.

[14]  Udo Mahlstedt,et al.  DIATEST: a fast diagnostic test pattern generator for combinational circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[15]  R. D. Blanton,et al.  An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis , 2008, 2008 IEEE International Test Conference.

[16]  Paolo Prinetto,et al.  A diagnostic test pattern generation algorithm , 1990, Proceedings. International Test Conference 1990.

[17]  Paolo Prinetto,et al.  GARDA: a diagnostic ATPG for large synchronous sequential circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[18]  Wojciech Maly,et al.  Fault tuples in diagnosis of deep-submicron circuits , 2002, Proceedings. International Test Conference.

[19]  R. D. Blanton,et al.  Multiple defect diagnosis using no assumptions on failing pattern characteristics , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[20]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Irith Pomeranz,et al.  Z-DFD: design-for-diagnosability based on the concept of Z-detection , 2004 .

[22]  Andreas G. Veneris,et al.  Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG , 2005, J. Electron. Test..

[23]  R. D. Blanton,et al.  Precise failure localization using automated layout analysis of diagnosis candidates , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[24]  Don Douglas Josephson,et al.  Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[25]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[26]  Thomas H. Cormen,et al.  Introduction to algorithms [2nd ed.] , 2001 .