Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues

New Design for Testability techniques aimed both at overcoming the problem of testing array architectures composed of sequential cells and guaranteeing fault tolerance through reconfiguration are proposed. Two strategies have been envisioned: (1) structural DfT techniques whose goal is to modify the interconnecting network embedding each cell, and (2) functional techniques aimed at defining a testable and reconfigurable implementation at the Finite State Machine (FSM) level and then synthesizing the modified functional description. Evaluation of the two classes of strategies on benchmarks are provided.

[1]  José A. B. Fortes,et al.  A taxonomy of reconfiguration techniques for fault-tolerant processor arrays , 1990, Computer.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Chia-Hsiaing Sung,et al.  Testable Sequential Cellular Arrays , 1976, IEEE Transactions on Computers.

[4]  Fabrizio Lombardi,et al.  Diagnosis of reconfigurable two-dimensional arrays using a scan approach , 1994, Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI).

[5]  T. Sridhar,et al.  Design of easily testable bit-sliced systems , 1981 .

[6]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[8]  Franco Fummi,et al.  Functional testing and constrained synthesis of sequential architectures , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[9]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[10]  Fabio Somenzi,et al.  Fast sequential ATPG based on implicit state enumeration , 1991, 1991, Proceedings. International Test Conference.

[11]  Mariagiovanna Sami,et al.  Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays , 1989 .

[12]  Irith Pomeranz,et al.  The Multiple Observation Time Test Strategy , 1992, IEEE Trans. Computers.

[13]  Franco Fummi,et al.  Design for testability issues in the implementation of sequential array architectures , 1994, Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI).

[14]  Kwang-Ting Cheng,et al.  A single-state-transition fault model for sequential machines , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.