Exploiting Behavioral Information in Gate-Level ATPG

This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level. The main problem is identified, namely the mismatch of timing models between the behavioral- and gate-levels. As a main contribution of this paper, a theoretical analysis of this problem led to the definition of a novel concept, that of dominated patterns, that captures the needed link between the levels. Some metrics are defined, taken from the software realm, that allow generation of test patterns at the behavioral-level. To validate the concept correctness, different ATPG systems are presented, and experimental results show an improvement in the test quality, thanks to the exploitation of behavioral-level information.

[1]  Paolo Prinetto,et al.  Testability analysis and ATPG on behavioral RT-level VHDL , 1997, Proceedings International Test Conference 1997.

[2]  Paolo Prinetto,et al.  GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Bruno Rouzeyre,et al.  High-level synthesis for easy testability , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[4]  Niraj K. Jha,et al.  Genesis: a behavioral synthesis system for hierarchical testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[5]  Elizabeth M. Rudnick,et al.  Fast sequential circuit test generation using high-level and gate-level techniques , 1998, Proceedings Design, Automation and Test in Europe.

[6]  Boris Beizer,et al.  Software Testing Techniques , 1983 .

[7]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[8]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[9]  Boris Beizer,et al.  Software testing techniques (2. ed.) , 1990 .