State Justification Using Genetic Algorithms in Sequential Circuit Test Generation

Complex VLSI circuits impose constraints on a test generator which are very difficult to handle using deterministic algorithms. Thus, a major goal in de­ veloping a new test generator is to have the capability of handling constraints, but without sacrificing the performance and effectiveness of deterministic ap­ proaches. In this paper, we describe a hybrid sequential circuit test generator which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justification. The hybrid test generator re­ stricts state justification for complex circuits to the genetic approach, which is better able to handle constraints. High fault coverages were obtained for the ISCAS89 sequential benchmark circuits and several synthesized circuits, and in many cases the results are better than those for purely deterministic approaches. Results were further augmented by preceding the hybrid test generation by a fast run of simulation-based test generation controlled by a genetic algorithm. T h is research was supported in part by ARPA under Contract DABT63-95-C-0069, in part by the Semiconductor Research Corporation under Contract SRC 94-DP-109, and in part by Hewlett-Packard under an equipment grant.

[1]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[2]  Melvin A. Breuer.  A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits , 1971, IEEE Transactions on Computers.

[3]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[4]  Miron Abramovici,et al.  Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") , 1994, Proceedings., International Test Conference.

[5]  Sudhakar M. Reddy,et al.  A new test generation method for sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[7]  Kwang-Ting Cheng,et al.  On the over-specification problem in sequential ATPG algorithms , 1992, DAC '92.

[8]  Michael H. Schulz,et al.  ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[9]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[10]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[11]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[12]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[13]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[14]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[15]  Hans-Joachim Wunderlich,et al.  Multiple distributions for biased random test patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[16]  Daniel G. Saab,et al.  Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0 , 1994, ICCAD.

[17]  Franc Brglez,et al.  Testability-Driven Random Test-Pattern Generation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Prathima Agrawal,et al.  A directed search method for test generation using a concurrent simulator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Kewal K. Saluja,et al.  An Efficient Algorithm for Sequential Circuit Test Generation , 1993, IEEE Trans. Computers.

[20]  Lalit M. Patnaik,et al.  A Simulation-Based Test Generation Scheme Using Genetic Algorithms , 1993, The Sixth International Conference on VLSI Design.

[21]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[23]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[24]  Thomas J. Snethen.  Simulator-oriented fault test generator , 1988, 25 years of DAC.

[25]  Elizabeth M. Rudnick,et al.  Application of simple genetic algorithms to sequential circuit test generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[26]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[27]  Elizabeth M. Rudnick,et al.  A genetic approach to test application time reduction for full scan and partial scan circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.