Radix-4 SRT 나눗셈 알고리즘의 하드웨어 구현 및 성능비교

In this paper, Radix-4 SRT division algorithm supporting IEEE-754 floating point standard and using in many of the micro-processor was verified and designed with Verilog HDL and C language. Radix-4 SRT division algorithm is α=2 and α=3 two type. In many of the micro-processor, it uses α=2. This is because, when α=2, it can be easily implemented by a d to 1bit shift. However, the circuit is complicated by the implementation of the 3 * d in the case of α=3. For each of α=2 and α=3, it was comparison of performance after a hardware implementation. As a result, The difference in the two types of circuit size was small. The operating speed in the case of α=2 was 0.47ns faster than α=3.