Programming disturbance and cell scaling in phase change memory: For up to 16nm based 4F2 cell

We focus here on the promising solutions to overcome thermal-induced erase failure of the unselected neighbor cell while a selected cell is being programmed to reset state with a high-current pulse. Our physical analysis directly demonstrate that this parasitic heating in Ge2Sb2Te5 based cell leads to partial crystallization in the amorphous reset state and to a consequent resistance decrease with disturbing current. Systematic approaches compatible with disturbance-free are addressed to achieve a highly scalable architecture, which can provide the physical and electrical criteria for phase change memory (PCM) up to 16nm technology node.