PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP

[1]  Chenming Hu,et al.  Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs , 2002 .

[2]  V. Trivedi,et al.  A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[3]  Ji-Woon Yang,et al.  A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits , 2004 .

[4]  J.G. Fossum,et al.  Bulk inversion in FinFETs and the implied insignificance of the effective gate width , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[5]  Michael Specht,et al.  Influence of crystal orientation and body doping on trigate transistor performance , 2006 .

[6]  K. Natori.  Ballistic metal-oxide-semiconductor field effect transistor , 1994 .

[7]  A. Di Carlo,et al.  Enhancement of the effective tunnel mass in ultrathin silicon dioxide layers , 2003 .

[8]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[9]  A. Asenov.  Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[10]  L. Selmi,et al.  Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[11]  T. Hiramoto,et al.  Mobility enhancement due to volume inversion in [110]-oriented ultra-thin body double-gate nMOSFETs with body thickness less than 5 nm , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[12]  S. Takagi,et al.  On the Universality of Inversion Layer Mobility in Si Mosfet's: Part 11-effects of Surface Orientation , 1994 .

[13]  P. Dollfus,et al.  Effect of discrete impurities on electron transport in ultrashort MOSFET using 3D MC simulation , 2003, IEEE Transactions on Electron Devices.

[14]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[15]  Ming-Fu Li,et al.  Metal gate work function engineering on gate leakage of MOSFETs , 2004, IEEE Transactions on Electron Devices.

[16]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[17]  A. Vandooren,et al.  CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET) , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[18]  Y. Akasaka,et al.  High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[19]  Yuan Taur,et al.  Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides , 1999, IBM J. Res. Dev..

[20]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[21]  J. Wortman,et al.  Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices , 1999 .

[22]  O. Gluschenkov,et al.  Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics , 2003, IEEE Electron Device Letters.

[23]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[24]  M. R. Khan,et al.  Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal–oxide–semiconductor transistors , 2002 .

[25]  Seung-Hwan Kim.  NONCLASSICAL NANOSCALE CMOS: PERFORMANCE PROJECTIONS, DESIGN OPTIMIZATION, AND PHYSICAL MODELING , 2006 .

[26]  Kevin J. Yang,et al.  Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices , 1999 .

[27]  J. Fossum,et al.  A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD , 1988 .

[28]  P. Solomon,et al.  Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness , 2003 .

[29]  C. Moglestue,et al.  Self‐consistent calculation of electron and hole inversion charges at silicon–silicon dioxide interfaces , 1986 .

[30]  S. Tiwari,et al.  Self‐consistent modeling of accumulation layers and tunneling currents through very thin oxides , 1996 .

[31]  Jerry G. Fossum,et al.  Nanoscale CMOS: potential nonclassical technologies versus a hypothetical bulk-silicon technology , 2005 .

[32]  M. Takayanagi-Takagi,et al.  Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[33]  J. An,et al.  Physical insights on design and modeling of nanoscale FinFETs , 2003, IEEE International Electron Devices Meeting 2003.

[34]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[35]  Gerard Ghibaudo,et al.  New method for the extraction of MOSFET parameters , 1988 .

[36]  Tohru Mogami,et al.  A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film , 2001 .

[37]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[38]  Price.  Resonant tunneling via an accumulation layer. , 1992, Physical review. B, Condensed matter.

[39]  G. Gildenblat,et al.  A surface potential-based compact model of n-MOSFET gate-tunneling current , 2004, IEEE Transactions on Electron Devices.

[40]  Leonard C. Feldman,et al.  Rapid thermal oxidation of silicon in N2O between 800 and 1200 °C: Incorporated nitrogen and interfacial roughness , 1994 .

[41]  J. J. Wortman,et al.  Rapid Thermal Oxidation of Silicon , 1986 .

[42]  V. Trivedi,et al.  Pragmatic design of nanoscale multi-gate CMOS , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[43]  S. Dimitrijev.  Principles of semiconductor devices , 2005 .

[44]  J. G. Fossum,et al.  Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs , 2002 .

[45]  P. V. Gray.  Tunneling From Metal to Semiconductors , 1965 .

[46]  Y.A. El-Mansy,et al.  A simple two-dimensional model for IGFET operation in the saturation region , 1977, IEEE Transactions on Electron Devices.

[47]  A comprehensive study of velocity overshoot effects in double gate silicon on insulator transistors , 2004 .

[48]  Keunwoo Kim,et al.  Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .

[49]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[50]  J.G. Fossum,et al.  On the feasibility of nanoscale triple-gate CMOS transistors , 2005, IEEE Transactions on Electron Devices.

[51]  T. Skotnicki,et al.  16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[52]  Y. Hou,et al.  Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices , 2002 .

[53]  F. Stern.  Self-Consistent Results for n -Type Si Inversion Layers , 1972 .

[54]  V. Trivedi,et al.  Suppression of corner effects in triple-gate MOSFETs , 2003, IEEE Electron Device Letters.

[55]  Bin Liu,et al.  Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits , 2001 .

[56]  A. Abramo,et al.  Modeling of electron mobility degradation by remote Coulomb scattering in ultrathin oxide MOSFETs , 2003 .

[57]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[58]  L. Selmi,et al.  An experimental study of low field electron mobility in double-gate, ultra-thin SOI MOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[59]  M. Lundstrom.  Fundamentals of carrier transport , 1990 .

[60]  Kaushik Roy,et al.  Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..