Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

Abstract Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics.

[1]  Heterodyn interferometer for the detection of electric and thermal signals in integrated circuits through the substrate , 1993 .

[2]  Dionyz Pogany,et al.  Time-resolved analysis of self-heating in power VDMOSFETs using backside laserprobing , 1997 .

[3]  Michael C. Smayling,et al.  Device integration for ESD robustness of high voltage power MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[4]  Sergey Bychikhin,et al.  Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry , 2002 .

[5]  Bruno Murari,et al.  Smart Power ICs , 1996 .

[6]  Steven T. Peake,et al.  Power semiconductor devices , 1995 .

[7]  Dionyz Pogany,et al.  Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique , 2000 .

[8]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[9]  Dionyz Pogany,et al.  A differential backside laserprobing technique for the investigation of the lateral temperature distribution in power devices , 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).

[10]  R. Soref,et al.  Electrooptical effects in silicon , 1987 .

[11]  G. Krieger,et al.  Thermal response of integrated circuit input devices to an electrostatic energy pulse , 1987, IEEE Transactions on Electron Devices.

[12]  M. Stecher,et al.  Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).